ASIC Design & Verification Glossary (2025 Edition)

A chip designed for a specific application or function, offering optimized performance, power efficiency and cost compared to general-purpose processors.

The full lifecycle of defining, architecting, implementing and validating an custom integrated circuit tailored for a targeted use case.

The process of checking that the ASIC design matches its specification, using techniques like simulation, formal methods and hardware acceleration.

The process of verifying the correct interaction between analog and digital components in a mixed signal SoC.

A modular silicon block that forms part of a larger multi-die system. Chiplets enable flexibility, yield improvement and faster time-to-market in advanced packaging.

The main processing element of a system responsible for executing instrutions and managing control flow and arithmetic operations.

Widely used programming languages in embedded systems and testbench environments. Commonly used alongside hardware description languages in DV workflows.

The creation of digital logic circuits using HDL languages like Verilog or VHDL, and synthesizing them into physical gates for fabrication.

A high-level hardware verification language used with the Specman tool from Cadence, designed for complex constraint-random verification.

Running the ASIC design on dedicated hardware (i.e. FPGA-based platforms) to accelerate functional verification and software development.

A suite of tools and methodologies used for designing, verifying and testing electronic systems including ASICs, FPGAs and PCBs.

A programmable silicon device used for prototyping, emulation, or low-volume production of digital logic designs.

Accelerates functional verification using hardware platforms like FPGAs or emulators, enabling faster simulation cycles for large, complex designs.

Languages like Verilog or VHDL used to model and simulate electronic systems.

A static code analysis technique that checks HDL code for syntax issues and potential design bugs before simulation or synthesis.

The physical production of ASICs at a semiconductor foundry, involving steps like photolithography, etching, deposition and packaging.

A SystemVerilog verification framework that laid the foundation for Univeral Verification Methodology (UVM).

Building a functional model of the ASIC to validate the logic behaviour before tape-out.

A high-speed serial communication protocol widely used in SoCs for interconnection components.

An abstraction level in digital circuit design where the system is defined in terms of data transfers between registers under clock control.

An open-source instruction set architecture (ISA) that supports custom SoC development with flexibility and scalability.

A single-chip solution that integrates CPU cores, memory, peripherals and more into one compact design.

A block that serializes and deserializes digital data, critical in high speed applications.

A combined hardware description and verification language commonly used in the EDA (electronic design automation) industry.

A Cadence EDA tool for advanced verification of complex SoCs, often used in conjunction with SystemVerilog and UVM.

The last stage in the ASIC design process when the layout is completed and sent to the foundry for fabrication.

A simulation environment generates stimulus and checks the outputs of the design under test (DUT) .

A standardized SystemVerilog framework that promotes reusable, scalable and modular verification environments for complex ASICs and SoCs.

Post-silicon activities that confirm whether or not the manufactured chip meets its requirements.

The pre-silicon process of ensuring a design conforms to its specification using simulation, emulation, formal methods and so on.

A foundational HDL (hardware description language) for modeling digital systems, widely used in RTL design and simulation.