If you work in ASIC design, verification or the broader Electronic Design Automation (EDA) ecosystem, DVCon Europe 2025 should be on your radar. Held in Munich, Germany on October 14 – 15, this year’s conference promises to deliver valuable insights, cutting-edge research and unmatched networking opportunities with industry leaders.
With submission deadlines fast approaching, now is the time to think about getting involved – whether you’re sharing your work, delivering a tutorial or attending to learn and connect.
What is DVCon Europe?
DVCon Europe (Design and Verification Conference Europe) is a leading technical conference focused on:
- System-level design and embedded software
- Functional and formal verification
- EDA methodologies and standards
Sponsored by the Accellera Systems Initiative, the conference brings together design and verification professionals who work at the intersection of hardware and software. Attendees can expect in-depth sessions, practical insights and a collaborative atmosphere.
How to Participate: Formats, Submissions & Deadlines
DVCon Europe 2025 welcomes submissions in three main categories. Here’s how you can get involved:
1. Engineering Papers
Share real-world case studies or explore emerging trends in ASIC design and verification.
Review process:
- Stage 1: 2 page abstract
- Stage 2: If accepted, a full 6 – 8 page technical paper
2. Research Papers
Present original, unpublished research with clear scientific contributions and evaluations.
- Max 6 pages
- Undergoes double-blind peer review
- Accepted papers will be published in IEEE Xplore
3. Tutorials
Submit a 1 – 3 page proposal for an educational sessions. Focus on real-world applications, best practices, and methodology using EDA tools and languages.
Key Submission Deadlines for DVCon Europe 2025
| April 27th, 2025 | Abstract submission for Engineering Papers |
| May 26th, 2025 | Author notification for Engineering Abstracts & Tutorials Proposals |
| June 30th, 2025 | Full submission deadline (Engineering Paper, Research Paper & Tutorial Drafts) |
| August 25th, 2025 | Final author notification (Full Papers & Tutorials |
| September 18th, 2025 | Registration, Signed Copyright Form, Camera Ready Paper & Final Tutorial Slides |
Visit the official DVCon Europe 2025 website to access templates, detailed guidelines and submission forms.
2025 Focus Areas: What’s on the Agenda?
This year’s conference focuses on the technologies and challenges shaping the future of chip design and verification. Anticipated focus areas include:
- System-level & Software Design
- Verification & Validation
- Mixed-Signal & Low Power Design Verification
- AI/ML & Big Data
- Functional Safety & Security
- IP Reuse & Design Automation
- Processor Ecosystem Developments
- Model-based Systems Engineering
DVCon Europe 2025 offers deep technical content and practical relevance that’s perfect for engineers tackling real-world challenges across ASIC and SoC development.
Program Highlights for 2025
DVCon Europe always has a lot to offer and this year’s program is no different. The highlights so far include:
Keynote: We Didn’t Start the Fire…Open Source Software in 2025
Delivered by OpenUK CEO, Amanda Brock, this keynote promises a dynamic dive into the evolution of open source software and the shift in digital infrastructure in the last 10 years. From AI to deep tech and geopolitics, Amanda unpacks 30 years of digital transformation through the lens of global collaboration and open source innovation.
Join the SystemC Modeling Challenge
Put your skills to the test in this year’s DVCon Europe Modeling Challenge. Participants will estimate the power consumption of a small application using a SystemC model. All successful participants receive a certificate of appreciation and there’s lots of Huawei smart tech prizes on offer for the winners! A dedicated session during the conference will showcase participants’ modeling approaches and insights.
Why Attend DVCon Europe 2025?
Participating in DVCon Europe 2025 is an excellent way to boost your visibility in the ASIC and verification community. Whether you’re presenting new ideas, joining technical tutorials, or networking with EDA leaders, this event offers:
- Direct feedback from peers and industry experts
- A platform to showcase your latest research or innovations
- Insight into standards like SystemVerilog, UVM and SystemC
- Access to a collaborative network of likeminded professionals
Ready to Join?
Whether you’re contributing a paper, registering to attend, or exploring sponsorship opportunities, DVCon Europe 2025 makes it easy to get involved.
- Visit the DvCon website: dvcon-europe.org
- Stay updated on Linkedin: DVCon Europe
- Review the full Call for Contributions
- Explore the official Registration Info
Stay tuned for more agenda updates, detailed event info and speaker announcements.