Your Quick Guide to DVCon Europe 2025
DVCon Europe 2025 kicks off this week, taking place October 14th – 15th in Munich, Germany, with the 10th SystemC Evolution Day following on October 16th.
For engineers working in ASIC design, functional verification, or system-level modelling, this is one of the must-watch events of the year.
In this quick guide, we explore what to expect from the 2025 conference – including the keynotes, tutorials, technical sessions and SystemC Evolution Day highlights.
What is DVCon Europe?
DVCon (Design and Verification Conference) Europe is an annual event focused on the practical use of design and verification technologies and methodologies. It’s tailored for:
- Chip architects
- Design and verification engineers
- System integrators
- EDA tool users and developers
- Standards contributors (SystemVerilog, SystemC, UVM, PSS, UPF)
The two day event combines high-value technical content with opportunities to engage directly with tool vendors, researchers and industry peers.
Keynotes: Open Source, AI & Automotive Innovation
- Keynote #1 – We Didn’t Start the Fire…Open Source Software in 2025: Amanda Brock, CEO of OpenUK, will explore the evolution of open source infrastructure, exploring its rise over the past three decades and its deep-rooted influence in modern technology. The keynote will connect the dots between open source adoption, geopolitical factors, AI and software sovereignty – offering engineers valuable context for understanding the forces shaping modern digital infrastructure.
- Keynote #2 – Driving Forward: The Evolution of Virtual Development in the Automotive Industry: From digital twins to hardware/software co-design, this keynote examines how virtual environments are transforming the automotive product lifecycle. It’s especially relevant for engineers developing ADAS, functional safety systems or those working in model-based design.
2025 Panel – Beyond the Chip: How Ecosystems Are Shaping the Future of System Design
This year’s featured panel will bring together experts from across the semiconductor value chain to explore how system design ecosystems are evolving, and look at why they’re becoming central to innovation across industries.
The discussion will dive into the multifaceted world of “system-of-systems” solutions, examining how collaborative ecosystems provide the tools, methodologies and frameworks that enable efficient and scalable development.
The panel will also discuss the challenges and future trends shaping system-level design, including AI and ML integration, edge computing and sustainability.
Tutorials: Deep Dives into Design & Verification
This year’s program includes more than 15 technical tutorials, each offering a 90 minute deep dive into critical areas of chip design and verification. Topics span AI-enhanced verification, low power design, processor verification and more.
Top Picks:
- Data-Driven Approach to Accelerate Coverage Closure on Highly Configurable ASIC Designs
- Next-Gen Verification Technologies for Processor-Based Systems
- Pre-Silicon Performance Benchmarking with Emulation Hybrids
- Tutorial on the Improvement introduced by IEEE 1801-2024 (UPF4.0) Standard for the Specifications, Implementation and Verification of Low Power intent
- Unleashing the Potential of AI Within Functional Verification
- Expediting Coverage Closure in Digital Verification with the Portable Stimulus Standard (PSS)
- Teaching Analog CMOS Chip Design using Open Source Tools
- Will it Blend? – Verifying the Hardware / Software Interface of complex SoCs
Whether you’re exploring the potential of machine learning in EDA or training the next generation of verification engineers, these sessions promise practical insights and hands-on learning relevant to today’s verification workflows.
SystemC Evolution Day 2025 (October 16)
Held the day after DVCon Europe ends, SystemC Evolution Day 2025 celebrates its 10th anniversary with a focused technical agenda on system-level modeling and simulation frameworks.
Key topics:
- Advances in Transaction-Level Modeling (TLM)
- Interoperability with FMI (Functional Mock-up Interface)
- SystemC-AMS for analog/mixed-signal co-simulation
- Applications in virtual prototyping and digital twins
If your work involves architecture exploration, co-simulation or multi-domain system design, this is an essential follow-up to the main conference
Final Thoughts
With its strong focus on practical methodologies, AI-driven verification, and open standardisation, DVCon Europe 2025 promises valuable insights for engineers and technical leaders across the semiconductor industry.
Whether you’re attending in Munich or following the highlights online, this year’s event offers a wealth of technical content designed to move verification and design forward – one innovation at a time.