Synopsys Showcases AI-Powered Engineering at DAC 2026
At this year’s DAC Chips to Systems Conference, Synopsys unveiled new AI-powered engineering capabilities that demonstrate how autonomous workflows and intelligent automation are reshaping semiconductor design and verification.
The announcements build on the company’s growing focus on agentic AI, with solutions designed to support engineers across the chip development lifecycle, from RTL design and verification to system-level engineering.
AI Takes on More of the Engineering Workflow
Rather than simply helping engineers complete individual tasks, Synopsys’ AI technologies are designed to coordinate multiple stages of the design flow. They support activities including RTL development, verification planning, test generation, debug and design optimisation.
Synopsys also showcased continued progress with AgentEngineer™, its agentic AI technology that enables long-running engineering workflows across design and verification. As semiconductor projects become increasingly complex, these capabilities aim to reduce repetitive manual work while allowing engineers to focus on higher-value design decisions.
A Connected Silicon-to-Systems Approach
Alongside its AI capabilities, Synopsys demonstrated its broader silicon-to-systems engineering strategy, bringing together chip design, verification, advanced packaging, simulation and software development within a more connected workflow.
The company also highlighted collaborations with industry partners, including NVIDIA, to accelerate AI-driven engineering using high-performance computing and generative AI technologies. Together, these developments reflect the growing role of AI as an integrated part of modern electronic design automation (EDA), rather than a standalone productivity tool.
Why It Matters for ASIC Design and Verification
While many AI announcements have focused on coding assistants or productivity tools, the latest developments from Synopsys point towards a broader transformation in semiconductor engineering. AI is increasingly being embedded into core EDA workflows to help manage growing design complexity, accelerate verification and improve engineering efficiency.
For ASIC teams, this could mean faster verification planning, more efficient debugging and greater automation of repetitive tasks, helping engineers spend more time solving complex design challenges.
As AI capabilities continue to evolve, the announcements at DAC 2026 reinforce a broader industry trend: embedding intelligent automation into every stage of semiconductor engineering. For ASIC teams, AI is becoming an integral part of the design and verification workflow rather than simply another productivity tool.