Industry News Highlights – July 2026
July was another busy month for the semiconductor industry, with AI continuing to influence almost every part of the chip development ecosystem, from custom silicon and advanced manufacturing to EDA, verification and autonomous engineering workflows.
Partnerships and acquisitions were also a major theme, as semiconductor companies looked to strengthen their capabilities across AI hardware, chip design, verification and manufacturing.
Here are some of the key semiconductor industry developments from July 2026.
AI Chip Design, Startups & Investment
OXMIQ raises $35 million to scale its OxCore architecture
OXMIQ Labs closed a $35 million Series A round, bringing its total funding to $60 million. The company is developing licensable GPU and AI architecture designed to allow semiconductor companies and AI system builders to develop custom AI silicon without undertaking a complete chip programme from scratch.
Signaloid previews new ASIC for physical AI
Signaloid announced a preview of its Co-ASIC, a chip designed for physical AI, robotics and probabilistic computing workloads. The ASIC was taped out with TSMC in partnership with IC-Link by imec and Cadence, with Signaloid projecting significant performance-per-watt improvements for targeted workloads.
Meta presents new Vistara ASIC research
Meta researchers presented work on Vistara, highlighting continued efforts to develop specialised silicon for large-scale AI infrastructure. The work reflects the broader industry trend towards custom accelerators designed around the specific requirements of hyperscale AI workloads.
ChipAgents raises $60 million
Chip design startup ChipAgents secured an additional $60 million in Series A2 funding, bringing its Series A financing to $134 million. The company is developing agentic AI tools for semiconductor engineering, with a particular focus on design, verification and debugging.
Industry Partnerships & Collaborations
Broadcom and Apple extend chip partnership to 2031
Broadcom and Apple expanded their long-standing technology collaboration through 2031, including agreements covering the development and supply of custom ASIC silicon for multiple generations of Apple products. The deal reinforces Broadcom’s position as a major supplier of Apple’s custom silicon.
Arteris and IC-Link by imec collaborate on next-generation AI and HPC silicon
Arteris announced a collaboration with IC-Link by imec to accelerate the development of AI and high-performance computing chiplets and ASICs. Arteris’ network-on-chip IP will be incorporated into IC-Link’s design and manufacturing services, helping customers reduce infrastructure development effort and increase design reuse.
Arteris and Arm expand hardware security partnership
Arteris expanded its partnership with Arm to extend hardware security assurance across additional Arm CPU programmes. The collaboration builds on five years of work using Arteris’ security assurance technology to identify potential vulnerabilities in processor designs.
Intel collaborates with Fortinet on custom silicon
Intel Foundry announced a collaboration with Fortinet to co-develop and manufacture Fortinet’s next-generation Security Processor 6. The engagement represents another step in Intel’s efforts to expand its external foundry and custom silicon business.
Rapidus and Cadence partner on advanced SoC design
Rapidus announced a collaboration with Cadence aimed at supporting advanced SoC development, strengthening the design ecosystem around Rapidus’ next-generation semiconductor manufacturing technology.
Samsung and Broadcom expand AI semiconductor collaboration
Samsung Electronics and Broadcom signed an MOU expanding their strategic collaboration across memory, foundry and advanced packaging technologies. The collaboration is expected to represent more than $200 billion in activity across the five years through 2030, reflecting the scale of investment required to support next-generation AI infrastructure.
AI-Powered EDA & Autonomous Engineering
Cadence unveils fully autonomous virtual engineer
Cadence announced its ChipStack AI Super Agent at Level-5 autonomy, designed to independently execute complex chip design and verification workflows. The system can work across specification understanding, RTL generation, verification planning, formal analysis, simulation, debugging and design convergence. Cadence reports that early deployments can reduce a typical five-week verification loop to less than a day.
Siemens and NVIDIA advance self-verifying agentic AI for EDA
Siemens expanded its strategic partnership with NVIDIA to deliver self-verifying agentic AI workflows for semiconductor and PCB design. The approach combines Siemens’ physics-based EDA tools with NVIDIA AI infrastructure, enabling autonomous agents to continuously validate their decisions against established engineering tools.
NVIDIA uses Vera CPU to accelerate chip design
NVIDIA announced that its Vera CPU is being deployed across EDA workflows used to develop future NVIDIA CPUs and GPUs. Early testing showed up to 1.5× higher performance on selected verification and simulation workloads, with optimisation work involving EDA leaders Cadence and Synopsys.
Synopsys, NVIDIA, AMD and Microsoft advance agentic chip design
Synopsys announced new autonomous EDA workflows developed with Microsoft and used by AMD, with the workflows available for evaluation through Microsoft Discovery. Initial results for an autonomous debug-closure workflow demonstrated up to a 40% reduction in cycle time.
Siemens adds AI-powered characterisation capabilities
Siemens announced agentic AI capabilities for its Solido Characterization Suite, designed to automate library characterisation and design iteration. The company reported reductions of more than 10× in characterisation turnaround times for targeted workflows.
ChipAgents expands semiconductor engineering deployments
ChipAgents reported new deployments with companies including Ambiq and Whalechip, demonstrating the growing application of agentic AI to real-world chip design, verification and debugging workflows. In one Whalechip deployment, the platform helped reduce root-cause analysis from days to between 15 and 60 minutes.
Technical Reads & Research Highlights
Looking to go beyond the headlines? Here are some of July’s interesting technical reads covering AI, verification, chiplets, RISC-V, mixed-signal design and the future of semiconductor engineering.
| Title | Source |
|---|---|
| An AI Model Fit For Purpose | SemiEngineering |
| We’re One Step Closer to Drag-and-Drop Off-the-Shelf Chiplet-Based Design | EE Journal |
| Accelerating AMS Verification With Mixed-Signal Visualizer | SemiEngineering |
| Why 28nm is the New Strategic Node? | Design & Reuse |
| Preparing For AI-Driven Chip Design And Verification | SemiEngineering |
| How Industrial AI is Different and Why the Distinction Matters | Siemens |
| Designing Electro-Optical Chips | SemiEngineering |
| Silicon Meets Reality: Why Physics Is Now a First-Order Design Constraint for Chips | Synopsys |
| The Impact Of AI Automation On Chip Design | SemiEngineering |
| RISC-V Is Inevitable, State of the Union Keynote Argues | EE Times |
| From Future Vision To Running Hardware: Verification At DAC 2026 | SemiEngineering |
| Adaptive Hardware Could Change How EV Chargers Are Designed | EE Times |
Looking Ahead
From autonomous verification agents and AI-powered EDA platforms to specialised accelerators, custom ASICs and increasingly sophisticated multi-die architectures, semiconductor engineering is evolving rapidly.
For verification engineers in particular, the growing adoption of agentic AI could have a significant impact on how engineers approach simulation, debug, coverage and verification closure. Rather than simply automating individual tasks, the latest tools are increasingly designed to reason across entire workflows — potentially changing the role of the engineer from executing individual processes to supervising and validating increasingly autonomous systems.
As we move further into the second half of 2026, it will be interesting to see which of these technologies move from demonstrations and early deployments into everyday semiconductor engineering workflows.
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