Keeping up with recent research can help ASIC and design verification engineers stay informed about new methodologies, tools and approaches across the verification lifecycle. This reading list brings together recent technical papers for ASIC verification, covering formal verification, pre-silicon validation, AI-assisted workflows and hardware security.
We’ve selected a few recent technical papers that are particularly relevant to engineers working across RTL, UVM, formal verification, emulation, SoC validation and hardware security.
| Technical Paper | Source |
|---|---|
| HW Information-Flow Tracking for Pre-Silicon Security Testing | Click Here |
| Modular Verification of RTL Processors Against ISA Contracts | Click Here |
| LLM-driven, Formal Verification-Assisted Framework for Functional-Safety-Oriented Fault Criticality Assessment | Click Here |
| Pre-Silicon Verification And Validation Methodology Targeting Robust RISC-V Chip Designs | Click Here |
| Leveraging Agentic AI Techniques To Improve Formal Verification | Click Here |
| Emulation-based System-on-Chip Security Verification: Challenges and Opportunities | Click Here |
| Extending Formal Verification To Sequential Circuits | Click Here |
| Information Flow Verification Framework Integrating Static and Formal Verification Methods at the Pre-Silicon Stage | Click Here |
For ASIC and SoC verification engineers, following this research provides useful context for understanding where verification methodologies are heading and which emerging techniques may eventually become part of practical verification workflows.
Looking for more technical resources? Explore Semiconductor Engineering’s technical paper roundups for further research across design verification, formal methods, hardware security and semiconductor design.