The Verification & Semiconductor Futures USA 2026 conference series is coming to the United States this October, bringing together design verification engineers, semiconductor professionals, researchers and technology providers for two one-day events in Austin and San Jose.
The 2026 programme places particular emphasis on areas shaping modern verification workflows, including:
- Formal Verification
- Artificial Intelligence in Design Verification
- RISC-V
- Open-source EDA
The events are co-located with Semiconductor Futures 2026 and are organised by Tessolve and Alpinum. Both conferences will be available to attend in person or online.
Verification Futures USA 2026 at a glance
| Event | Date | Location | Format |
|---|---|---|---|
| Verification & Semiconductor Futures Austin | 6 October 2026 | Hilton Austin Airport, 9515 Hotel Dr, Austin, TX 78719, United States | In person & online |
| Verification & Semiconductor Futures San Jose | 8 October 2026 | Sonesta San Jose – Milpitas, 777 Bellew Dr, Milpitas, CA 95035, United States | In person & online |
Both conferences run from 08:30 to 17:00 and combine technical presentations, parallel sessions and networking opportunities.
What is Verification Futures?
Verification Futures is a conference series focused on the challenges facing hardware and software verification as semiconductor systems become increasingly complex.
The Verification Futures programme includes:
- Advanced EDA Tools & Technologies
- Latest Research From Universities
- Expert Talks & Training
- Product & Engineering Experts
The co-located Semiconductor Futures programme expands the discussion into AI and semiconductor design, emerging hardware technologies, FPGA, mixed-signal design, AI design IP and new technologies including quantum computing and photonics.
Key themes at Verification Futures USA 2026
Several themes stand out across the 2026 US programmes:
- Formal Verification and AI
- Emerging Hardware Technologies
- Using AI in VLSI & DV
- Open-Source EDA and Verification Tools
- AMS Design & Verification
- CDC-RDC Verification
- Verification of Complex Systems
The combination of these topics reflects the increasingly broad role of verification within modern semiconductor development, from block-level verification through to complex SoC and system-level validation.
What’s on the lineup?
The speaker lineup spans EDA vendors, semiconductor companies, technology companies, universities and independent specialists.
Verification & Semiconductor Futures Conference San Jose 2026
The San Jose conference takes place on Thursday, 8 October, at Sonesta San Jose – Milpitas. The programme includes dedicated sessions covering formal verification and AI, AMS design and verification, open-source approaches, emerging hardware technologies and complex-system verification.
A selection of speakers includes:
| Topic | Speaker |
|---|---|
| Formal Verification and AI | Tobias Ludwig, LUBIS EDA |
| AMS Design and Verification | Leon King, Cadence Design Systems |
| Using AI and Open Source in DV | Oscar Gustafsson, Linköping University |
| Emerging Hardware Technologies | Allen Nejah, SunMan Engineering |
| CDC-RDC Verification Tutorial | Bill Gascoyne, Blue Pearl Solutions Dammy Olopade Google |
Verification & Semiconductor Futures Conference Austin 2026
The Austin conference takes place on Tuesday, 6 October, at Hilton Austin Airport. Its verification programme includes sessions on formal verification and AI, AI in VLSI and design verification, AMS design and verification and emerging hardware technologies.
A selection of speakers includes:
| Topic | Speaker |
|---|---|
| Formal Verification and AI | David Landoll, Siemens |
| Emerging Hardware Technologies | Praveen Kumar Vagala, Independent Researcher |
| Using AI in VLSI & DV | Sunil Sahoo, Siemens EDA |
| AMS Design and Verification | Daniel Cross, Cadence Design Systems |
| Using AI in VLSI & DV | Shelly Henry, Moores Lab AI |
How to register for Verification Futures USA 2026
Both US conferences are currently listed as free to attend, with in-person and online attendance available. Advance registration is required.
Austin takes place on Tuesday, 6 October 2026, at the Hilton Austin Airport. The event is available in person and online via Microsoft Teams.
San Jose takes place on Thursday, 8 October 2026, at Sonesta San Jose – Milpitas. It is also available both in person and online via Microsoft Teams.
Registration links
Austin: Register through the official Verification & Semiconductor Futures Austin 2026 event page.
San Jose: Register through the official Verification & Semiconductor Futures San Jose 2026 event page
Looking ahead to Verification Futures USA 2026
With two US events taking place in the same week, Verification & Semiconductor Futures USA 2026 provides a broad view of the issues currently shaping semiconductor verification.
From formal methods and AI-assisted DV to open-source EDA, complex systems and emerging hardware technologies, the programme reflects a verification landscape that is becoming increasingly connected to the wider semiconductor development process.
For engineers working across ASIC design, design verification, formal verification, FPGA, SoC development or hardware/software integration, the events offer an opportunity to follow current engineering discussions and compare approaches with practitioners across the industry.