Keeping up with the latest ASIC design and verification research can be overwhelming. From AI-driven automation and LLM-assisted RTL generation to high-throughput architectures and advanced security frameworks, 2025 has delivered remarkable breakthroughs. To save you time, we’ve curated some of the most impactful technical papers of the year, highlighting research that VLSI engineers, chip designers and verification specialists can apply to real-world silicon development.
PlaceIT: Placement-based Inter-Chiplet Interconnect Topologies
2.5D integration technology is gaining traction as it copes with the growing design cost of modern ICs. This paper presents PlaceIT; a new methodology that jointly optimises inter-chiplet interconnect topology and chiplet placement, reducing latency and improving throughput for critical traffic types.
Accelerating Pre-Silicon Verification Coverage with Transaction Sequence Modeling
Pre-silicon verification is key to catching design errors early, but simulation cycles can be time-consuming. This paper proposes using UVM transaction sequences to train machine learning models that predict which simulations are likely to improve code or functional coverage. By selectively running only impactful simulations, the method accelerates coverage and optimises verification resources, as demonstrated on two Designs-Under-Test (DUTs).
Digital Twin Technologies for Vehicular Prototyping: A Survey
Digital Twin (DT) technology creates dynamic virtual replicas of vehicles and components, enabling advanced simulation, real-time monitoring and enhanced performance and safety. This paper reviews DTs and other prototyping approaches for smart vehicular systems across automotive, aviation and maritime domains.
Generative AI for Analog Integrated Circuit Design: Methodologies and Applications
This paper reviews recent advances in applying generative AI to analog IC design, including graph neural networks, large language models and variational autoencoders. It highlights methods addressing data scarcity, topology exploration, process-voltage-temperature (PVT) variations and layout parasitics, providing guidance for researchers and engineers.
FastPath: A Hybrid Approach for Efficient Hardware Security Verification sign: Methodologies and Applications
FastPath is a hybrid verification methodology combining simulation efficiency with formal verification exhaustiveness to detect micro-architectural information leaks. The approach focuses on automating structural analysis, reducing manual effort and maintaining rigorous security verification – as demonstrated on a RISC-V processor.
Hierarchical Formal Verification and Progress Checking of Network-On-Chip Design
Formal verification is essential for ensuring the correctness of complex Network-on-Chip (NoC) designs, but traditional approaches often focus on isolated functionalities. This paper introduces a hierarchical, divide-and-conquer formal verification methodology with multi-level abstraction, enabling comprehensive verification across all units. The approach demonstrates how formal models and progress checking can support end-to-end formal signoff for complex SoC interconnect architectures.
VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation
This paper presents VerilogDB, a 20,392-sample Verilog dataset designed for training and fine-tuning large language models for RTL generation. The dataset is curated with preprocessing, syntax verification and metadata extraction, making it reportedly the largest high-quality resource for AI-assisted hardware design.
Solving the compute crisis with physics-based ASICs
This paper explores physics-based ASICs that leverage intrinsic physical dynamics for computation rather than enforcing traditional digital abstractions. These ASICs are said to offer substantial gains in energy efficiency and computational throughput, potentially accelerating AI workloads, neural network inference and scientific simulations.
FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors
FERIVer is an FPGA-assisted SoC platform that aims to accelerate RTL verification of RISC-V processors by combining instruction-level simulation with hardware emulation. This paper presents how it achieves up to 150x speed-up over vendor-specific tools and 35x over open-source setups, while maintaining low FPGA resource usage for cost and time efficient verification.
Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Dataset
SystemVerilog assertions are essential for ensuring correct SoC functionality – but manual generation remains a major bottleneck for engineers. This paper explores VERT, an open-source dataset that fine tunes open-source LLMs for automated assertion generation. Fine-tuned models like Deepseek Coder 6.7B and Llama 3.1 8B achieved up to 96.9% improvement over base models and 24% higher accuracy than GPT -4o, outperforming proprietary tools while preserving data privacy and eliminating costly licenses.
A Novel AI-ML Regression Flow for SoC verification
Verification can consume up to 65% of the total design cycle, with debugging often taking up more than half of that time. This paper proposes an AI-ML-driven regression flow featuring three main engines – CodeMiner, WaveMiner and the Defect Tracking Tool (DTT) – to automate root-cause analysis across large regression suites. The framework accelerates debug cycles by 10-20x, adapting to IP, subsystem and full SoC verification environments, significantly improving time-to-market efficiency.
Guardians of the Chip: Mastering Next-Gen Security for SoCs and IPs
This paper presents a Layered IDE Packet Security Framework designed to uncover and address verification blind spots in error detection, state transitions and protocol handling. By integrating modular debug hooks, flexible verification methods and state machine tracking, this framework achieved 97% verification coverage, strengthening both data integrity and SoC-level security.
Emerging Trends in ASIC Design & Verification
These papers showcase practical solutions to the challenges of modern chip development – from accelerating pre-silicon verification and leveraging LLMs for RTL and assertion generation to ensuring comprehensive security coverage in SoCs.
Bookmark this list to stay updated on cutting-edge ASIC research while continuing to explore ways to streamline your workflows, improve efficiency and future-proof your designs in an ever-evolving semiconductor ecosystem.