DVCon Europe 2026: What to Expect and Key Deadlines for Open Call Submissions
DVCon Europe is one of the most important events in the design and verification calendar, bringing together engineers, researchers and tool vendors focused on advancing verification methodologies.
If you work with SystemVerilog, UVM, formal verification or hardware-assisted verification, this is where many of the industry’s most practical insights are shared, not just theory, but real-world implementation experiences.
For engineers across Ireland, Europe and beyond, DVCon Europe is a chance to:
- Stay current with evolving verification methodologies
- Learn from real project case studies
- Connect with peers working on complex ASIC and SoC designs
What to Expect at DVCon Europe 2026
Hosted by Accellera Systems Initiative, the Design and Verification Conference & Exhibition Europe is scheduled to take place in Munich on the 17th and 18th November, 2026. While the full event program is still to be announced, DVCon Europe typically focuses on deep technical content with strong real-world relevance.
Attendees can typically expect:
- Peer-reviewed technical papers on advanced verification topics
- Tutorials and workshops led by experienced engineers
- Industry panels discussing emerging trends and challenges
- Vendor exhibitions showcasing the latest EDA tools and solutions
Open Call for Papers & Key Deadlines for Submission
If you’re considering submitting your work, DVCon Europe’s Call for Papers is a highly competitive process and a valuable opportunity to share your expertise with the wider community.
Application Areas of Interest
Submissions are encouraged across a wide range of industries, including:
- Automotive
- Mobile communication
- Aerospace
- Healthcare
- Chip-cards
- Consumer electronics
- Power electronics
Special Interest Topics
Key focus areas for 2026 include:
- Digital Twin
- Internet-of-Things (IoT)
- Functional Safety and Security
- Artificial Intelligence and Machine Learning
- ADAS
- Digitalisation
Important Dates and Deadlines
| Deadline for Engineering Abstracts and Tutorials Proposals | May 4th, 2026 |
| Author Notification Engineering Abstracts and Tutorial Proposals | June 15th, 2026 |
| Full Submission Deadline for Engineering Paper, Research Paper, and Tutorial Draft Slides | July 27th, 2026 |
| Research Papers – Full Submission Deadline | July 27th, 2026 |
| Author Notification Engineering Full Paper, Research Paper, and Tutorials | September 28th, 2026 |
| Accepted Papers – Camera Ready Final Manuscript & Registration Deadline for Accepted Papers/Poster | October 18th, 2026 |
Publishing at DVCon can:
- Strengthen your professional profile
- Showcase your work to leading companies
- Open up collaboration opportunities
If you’ve worked on a challenging verification problem or developed a novel methodology, it’s well worth considering.
DVCon Europe 2026 for Verification Engineers
DVCon Europe 2026 isn’t just another industry conference, it’s a focused opportunity to stay aligned with how ASIC design and verification are evolving in practice.
With growing design complexity, tighter timelines, and the increasing role of AI-driven workflows, events like DVCon Europe provide an opportunity to step back and see how others are solving similar problems.
As the 2026 Call for Papers deadlines approach, now is the time to decide whether you want to contribute, attend or simply follow the technical output. For verification engineers trying to stay ahead of industry trends, this is always an event worth keeping an eye on.