Semiconductor News Roundup: October 2026
October has brought further developments in AI-driven chip design, custom silicon and semiconductor verification. EDA vendors are expanding agentic AI capabilities, hyperscalers are investing in specialised processors and networking hardware, and industry discussions are increasingly focused on verification, intellectual property and the cost of developing advanced computing systems.
This month’s roundup covers the latest developments in semiconductor design, manufacturing, verification and AI infrastructure, alongside news relevant to Ireland’s technology ecosystem.
Semiconductor News Headlines
Synopsys expands agentic AI across semiconductor engineering
Synopsys is expanding its AgentEngineer portfolio and Autopilot platform to coordinate multi-step engineering workflows across verification, physical implementation, analog design, manufacturing and simulation. The approach aims to move beyond individual AI-assisted tasks towards agents that can plan, execute and refine engineering workflows using established design tools.
Keysight introduces agentic AI to design software
Keysight is introducing agentic AI capabilities to its electronic design software, allowing engineers to connect AI agents to RF design workflows through its Advanced Design System (ADS) 2027. Agents can generate and optimise circuit designs, while Keysight’s simulation tools validate their outputs. The approach is intended to help engineers evaluate more design alternatives without removing established engineering checks.
LUBIS EDA launches FormalOS for scalable formal verification
LUBIS EDA introduced FormalOS, a platform designed to make formal verification more systematic and scalable. It provides a tool-agnostic orchestration layer that brings formal engines, applications, automation and methodology into a unified environment, with optional AI integration. The launch reflects continued industry investment in improving verification workflows and achieving predictable RTL sign-off.
Meta details its next-generation AI networking infrastructure
Meta outlined its next-generation AI infrastructure, including high-bandwidth network switches, liquid-cooled networking racks and a unified fabric for large-scale AI workloads. Its approach combines custom infrastructure with silicon from Nvidia and Broadcom, illustrating how networking ASICs and specialised switching architectures are becoming increasingly important to the performance and scalability of AI data centres.
Ireland secures international backing for the Dublin Declaration on Trusted AI
The Government of Ireland announced international support for the Dublin Declaration on Trusted, Safe and Sovereign Artificial Intelligence following the International AI Summit in Dublin. The declaration promotes cooperation on AI safety, skills, research, computing infrastructure and technological capability. For Ireland’s semiconductor ecosystem, these priorities are relevant to the wider development of AI infrastructure and advanced technology expertise.
Vinci brings physics AI into the chip design process
At SEMICON West 2026, Vinci presented an approach to integrating physics-based AI into the semiconductor design process. By combining AI techniques with physical models and engineering constraints, the approach aims to help designers explore and evaluate potential solutions earlier in the development cycle. The development reflects broader efforts to make AI useful within engineering workflows where physical behaviour and measurable results remain essential.
Rambus and ChipAgents collaborate on AI-assisted chip design
Rambus and ChipAgents announced a strategic collaboration to integrate agentic AI into chip and silicon IP design workflows. The ChipAgents platform will be used to support design and IP integration, while also becoming a strategic investor in the company. The partnership reflects growing interest in applying AI across semiconductor development rather than limiting its use to isolated design tasks.
Siemens adds self-verification to long-running EDA agents
Siemens has expanded its EDA AI capabilities with workflows that allow agents to monitor long-running tasks, inspect results, respond to failures and retry operations. Rather than relying on an AI model alone to determine correctness, the approach uses established EDA engines, including simulation and verification tools, to validate engineering outputs. This distinction is important as AI agents take on increasingly complex design activities.
Agnisys and Axiomise collaborate on NoC design and formal sign-off
Agnisys and Axiomise have partnered to combine automated network-on-chip (NoC) generation with formal verification. Designs generated using Agnisys’ IDS-NoC technology can be verified using Axiomise’s nocProve, targeting complex AI processors, GPUs and inference chips. The collaboration aims to connect specification-driven design automation with formal sign-off to improve verification confidence and reduce development time.
Harmonic expands AI into chip design verification
Harmonic, the AI startup co-founded by Robinhood CEO Vlad Tenev, is expanding its Aristotle model into software and chip design verification. The move reflects increasing interest in using AI to reason about complex systems and identify potential errors. As these tools enter semiconductor workflows, their effectiveness will depend on how reliably they can support established verification processes.
ChipAgents expands its agentic AI platform across digital and analog design
ChipAgents announced an expansion of its platform across digital and analog chip design. The development builds on the growing use of AI agents to support multiple stages of semiconductor engineering, from design tasks to debugging and verification. Broader coverage across design domains could help teams integrate AI into more of their development workflows, provided that results remain subject to engineering validation.
Oracle brings Google TPUs to its cloud infrastructure
Oracle announced plans to offer Google Tensor Processing Units (TPUs) through Oracle Cloud Infrastructure, giving customers access to Google’s purpose-built AI accelerators outside Google’s own cloud. The agreement highlights the growing diversity of AI computing architectures available to data-centre operators and the strategic importance of custom silicon for training and inference workloads.
Technical Reads & Research Highlights
| Title | Source |
|---|---|
| Tracing Hardware Design From Physical Devices To RTL | Infineon via SemiEngineering |
| Validate AI Factory Changes with Digital Twins and AI Agents | Nvidia Developer |
| Chiplets at the Edge: How Modular SoCs Redefine Performance Per Watt | Embedded |
| Rising Costs, Compute Demand Push ADAS Toward Modular AI | EE Times |
| Scaling 3D IC design: Trends, Challenges and Practical Workflows | EE Times |
| Will AI Replace Semiconductor Engineers? 2026 Reality for Chip Design, Verification and Manufacturing | Alpinum |
| Agentic AI Automates RTL Waveform Analysis And Debugging | SemiEngineering |
| Why Are U.S. Hyperscalers Designing Their Own AI Chips, and What Does It Mean for ASIC Innovation? | Kings Research |
| AI Code Generation Doesn’t Solve Software Engineering | EE Times |
| Mastering Semiconductor Chip Design: Tools, Techniques, and Best Practices | Agnisys via Design & Reuse |
| Why Chip Design AI Benchmarks Must Go Beyond Functional Correctness | EE Times |
| Addressing chip design challenges with ADCs | Design & Reuse |
| Physics-Based Validation: The Foundation Of Trustworthy Agentic EDA | SemiEngineering |
| Rethinking Shift Left In Chip Design | SemiEngineering |
| Democratizing Chip Design: Empowering the Next Generation of Engineers with RISC-V Expertise | Design & Reuse |
Upcoming Events
| Date | Organiser | Event | Type | Location |
|---|---|---|---|---|
| November 9th 2026 | MIDAS Skillnet Ireland | Advanced Python 3 | Training | Online |
| November 10th 2026 | Siemens EDA | Beyond the Numbers: What the 2026 Functional Verification Study Reveals | Webinar | Online |
| November 13th 2026 | Doulos | cocotb – An Introduction for Python Programmers | Webinar | Online |
| November 17th 2026 | MIDAS Skillnet Ireland | SystemVerilog for Design | Training | Online |
| November 19th 2026 | MIDAS Ireland | Annual Conference & Gala Dinner 2026 | Conference | Limerick, Ireland |
| November 24th 2026 | Altera | Altera Innovators Day Event Series | Conference & Exhibition | Marlow, UK |
| December 2nd 2026 | Alpinum Events | Hands-on AI in Formal Verification Training | Training | Hybrid (Edinburgh, UK or Online) |
| December 2nd 2026 | Alpinum Events | AI in Physical Implementation (DV Club Edinburgh) | Training | Edinburgh, UK |
| December 8th – 9th 2026 | Design & Reuse | IP-SoC EU 2026 | Conference | Grenoble, France |
| December 9th – 10th 2026 | EE Times | AI Everywhere 2026 | Conference | Online |
For more events, explore our recent blog post: Q4 Semiconductor & ASIC Events Guide: Ireland & Europe 2026
Key Semiconductor Industry Trends to Watch
October’s semiconductor news highlights several important developments shaping the industry, particularly the growing use of AI in ASIC design, electronic design automation (EDA) and hardware verification. As semiconductor companies invest in custom AI accelerators, advanced-node manufacturing and automated engineering workflows, the complexity of chip development continues to increase.
For ASIC design and verification teams, these developments reinforce the importance of combining emerging AI capabilities with established engineering practices. Formal verification, functional validation and robust design methodologies remain essential to ensuring the reliability and performance of increasingly complex semiconductor devices.
As the industry moves towards more automated chip development, access to experienced semiconductor engineers and specialist design verification expertise will remain important in bringing advanced silicon from specification through to successful implementation.
Need support with ASIC design, design verification or semiconductor engineering? Get in touch with AsicPro to discuss your project requirements and explore how our experienced engineering teams can support your next development.