DVCon Europe 2026
As semiconductor designs become increasingly complex, design verification teams face growing challenges around verification coverage, system integration, functional safety and development timelines. These challenges will feature prominently at DVCon Europe 2026, taking place on 17–18 November in Munich, Germany.
The annual Design and Verification Conference brings together engineers, researchers, technology providers and industry specialists to examine developments in electronic design automation (EDA), design verification methodologies and semiconductor engineering.
With the 2026 program fully confirmed, several topics stand out, particularly the growing application of AI in verification, advances in formal verification, hardware-software co-verification and approaches to managing verification complexity.
For design verification engineers and engineering teams, these sessions offer an opportunity to explore practical methodologies, evaluate emerging technologies and consider how verification practices are evolving across the semiconductor industry.
DVCon Day 1 Program Overview
| Time | Session |
|---|---|
| 08:45 – 09:00 | Opening Session |
| 09:00 – 10:30 | 1A: Sponsor Tutorial – Cadence | Verification in the Agentic AI Era – A Whole New Ball Game! |
| 09:00 – 10:30 | 1B: Sponsor Tutorial – Chip Agents & Marvell | Scaling AI in Design Verification: From Agents to Systems |
| 09:00 – 10:30 | 1C: Sponsor Tutorial – Scientific Analog | Automated Equivalence Checking for Analog/Mixed-Signal Models |
| 09:00 – 10:30 | 1D: Sponsor Tutorial – Real Intent | Beyond Boolean Limits Next-Generation Static Verification for Microarchitectural Integrity, CDC, Connectivity, and Hardware Security |
| 10:30 – 11:00 | Morning Break |
| 11:00 – 12:30 | 2A: Sponsor Tutorial – Siemens | Agentic AI for Chip Design |
| 11:00 – 12:30 | 2B: Sponsor Tutorial – MathWorks | Engineers in the Loop: Generative and Agentic AI Semiconductor Workflows with MATLAB |
| 11:00 – 12:30 | 2C: Sponsor Tutorial – Arteris | Physically-Aware NoC Topology Design Automation |
| 11:00 – 12:30 | 2D: Sponsor Tutorial – Lubis | From Craft to System: A Platform Approach to Structured and Automated Formal Verification |
| 12:30 – 14:15 | Lunch |
| 14:15 – 15:45 | 3A: Sponsor Tutorial – Synopsys | Transforming Verification Debug: AI Innovations with Verdi |
| 14:15 – 15:45 | 3B: Sponsor Tutorial – Qblox | AI-Enhanced UVM Environment Generation from VHDL: Bridging Design and Verification with Machine Learning |
| 14:15 – 15:45 | 3C: Sponsor Tutorial – SK hynix | AI in Action: Improving Design Verification Workflow Through Smart Automation |
| 14:15 – 15:45 | 3D: Sponsor Tutorial – Breker | Processor Sub-System Verification: Different Techniques for Unique Scenarios |
| 14:15 – 15:45 | 3E: Sponsor Tutorial – Aedevices & NXP | UVM-MS in Practice: From the Accellera Baseline to Reusable Mixed-Signal Verification Architectures |
| 15:45 – 16:30 | Afternoon Break |
| 16:30 – 18:00 | 4A: User Tutorial – CPS Digital Twin | From Bench to Deployment: Building Deterministic Digital Twins of Cyber-Physical Systems with Frost and Lingua Franca |
| 16:30 – 18:00 | 4B: User Tutorial – Functional Safety | Automating Functional Safety: Introducing the Accellera FSL 1.0 Standard (Accellera FS-WG) |
| 16:30 – 18:00 | 4C: User Tutorial – Clock Domain Crossing | CDC-RDC Standardization: Challenges & Achievements |
| 16:30 – 18:00 | 4D: User Tutorial – Formal/simulation | A Hybrid Formal and Simulation Verification Methodology for Accelerated Coverage Closure |
| 19:00 – 22:30 | Conference Dinner |
DVCon Day 2 Program Overview
| Time | Session |
|---|---|
| 08:45 – 09:00 | Opening Session |
| 09:00 – 09:45 | Professor Hussam Amrouch Keynote: AI for Chips, Chips for AI — and the Growing Talent Gap in Between |
| 09:45 – 10:30 | Morning Break & Expo |
| 10:30 – 12:30 | 1A: Safety, Security, DFT & Design Automation | Multiple Presentations |
| 10:30 – 12:30 | 1B: Formal Verification, Coverage & Verification Methodology | Multiple Presentations |
| 10:30 – 12:30 | 1C: Processor, SoC & System-Level Verification I | Multiple Presentations |
| 10:30 – 12:30 | 1D: Protocol, Interface & Mixed-Signal Verification I | Multiple Presentations |
| 10:30 – 12:30 | 1E: AI/ML & Agentic Verification I | Multiple Presentations |
| 12:30 – 13:30 | Lunch & Expo |
| 13:30 – 14:15 | Antoine Madec Keynote: Perfection Is a Bad Idea: Pragmatic Verification of Complex ASICs at a Scale-Up |
| 14:15 – 14:30 | Break |
| 14:30 – 15:50 | 2A: Safety, Security, DFT & Design Automation II – Multiple Presentations |
| 14:30 – 15:50 | 2B: Formal Verification, Coverage & Verification Methodology II | Multiple Presentations |
| 14:30 – 15:50 | 2C: Processor, SoC & System-Level Verification II | Multiple Presentations |
| 14:30 – 15:50 | 2D: Protocol, Interface & Mixed-Signal Verification II | Multiple Presentations |
| 14:30 – 15:50 | 2E: AI/ML & Agentic Verification II | Multiple Presentations |
| 15:50 – 16:30 | Afternoon Break & Expo |
| 16:30 – 17:50 | 3A: Safety, Security, DFT & Design Automation III – Multiple Presentations |
| 16:30 – 17:50 | 3B: Formal Verification, Coverage & Verification Methodology III | Multiple Presentations |
| 16:30 – 17:50 | 3C: Processor, SoC & System-Level Verification III | Multiple Presentations |
| 16:30 – 17:50 | 3D: Protocol, Interface & Mixed-Signal Verification III | Multiple Presentations |
| 16:30 – 17:50 | 3E: AI/ML & Agentic Verification III | Multiple Presentations |
| 17:50 – 18:05 | Closing Sessions/Awards |
Verification Themes and Trends to Watch
The 2026 DVCon Europe program highlights several developments shaping semiconductor design verification, with a particularly strong focus on AI-driven methodologies, formal verification and increasingly complex system architectures.
AI and Agentic Verification
AI is one of the most prominent themes this year, with Day 1 tutorials from Cadence, Siemens, Synopsys, MathWorks and other industry participants exploring agentic AI, verification automation and AI-assisted debugging. Day 2 continues this focus with dedicated AI/ML and Agentic Verification presentation tracks, alongside Professor Hussam Amrouch’s keynote on AI and semiconductor development. The sessions offer insight into how AI could support verification planning, testbench development and debugging while maintaining engineering oversight and confidence in results.
Formal Verification, Coverage and Functional Safety
Formal verification and coverage closure remain important topics, particularly as increasing design complexity places greater demands on traditional simulation-based approaches. The program also addresses functional safety, hardware security and clock domain crossing, including a tutorial introducing the Accellera Functional Safety Language (FSL) 1.0 standard. These topics are particularly relevant to teams working on complex and safety-critical ASIC designs, where verification must extend beyond functional correctness.
SoC, System-Level and Mixed-Signal Verification
As SoC architectures become more interconnected, verification must account for interactions across processors, IP blocks, interfaces and hardware-software boundaries. DVCon Europe 2026 includes dedicated tracks covering Processor, SoC and System-Level Verification, alongside Protocol, Interface and Mixed-Signal Verification. These sessions provide an opportunity to examine approaches to validating complex architectures, integrating different design domains and improving verification across increasingly sophisticated systems.
Attending DVCon Europe 2026?
DVCon Europe 2026 takes place on 17–18 November at the Holiday Inn Munich City Centre in Munich, Germany. The conference brings together design and verification engineers, semiconductor companies, EDA providers and industry specialists for two days of technical presentations, tutorials and networking.
For the complete programme, registration information and event updates, visit the official DVCon Europe website.