Siemens EDA Launches Questa One Verification Tool for Faster SoC Design
At User2User in Munich, Siemens EDA unveiled Questa One – a unified, next-generation verification platform built to handle the rising complexity of SoC and ASIC designs in 2025 and beyond.
By combining advanced verification technologies under a single umbrella – and enhancing them with AI and automation – Questa One aims to reduce turnaround times and eliminate productivity bottlenecks across the verification flow.
From faster simulation to smarter debug and wider ecosystem compatibility, Siemens’ new platform points to a more scalable future for verification engineers, particularly those working with 3D-ICs, chiplet-based designs and software-defined architectures.
Designed for Complexity at Scale
As the complexities of modern chips continues to grow, verification engineers face immense pressure to validate architectures that stretch the limits of conventional toolsets From AI accelerators to domain-specific SoCs, today’s designs need verification strategies that are not only faster – but smarter, too.
Questa One is built to face these challenges:
“Questa One uses new technical advances to deliver the fastest functional, fault and formal verification engines available, yet customers tell us that performance alone isn’t enough – they also need deeper connectivity across our unmatched verification, validation and test workflows, which Questa One provides. Combined with our application of AI, Siemens’ verification solutions are truly yielding step-function gains in productivity by early adopters across smart creation, smart regression, smart analysis, smart engine and smart debug domains,”
said Abhu Kolpekwar, Vice President & General Manager, Digital Verification Technologies, Siemens EDA.
A Smarter Approach to Verification
The ultimate goal with Questa One is to close the longstanding verification productivity gap – a growing challenge for chip engineers as designs continue to scale in size and complexity. Leveraging AI and machine learning, it streamlines simulation, removes redundant test cases and enables faster coverage closure – all while maintaining high levels of accuracy.
Key highlights include:
- 50x faster coverage closure with Questa One Coverage Acceleration, featuring advanced UVM constrained random test generation
- 8x faster gate-level DFT simulation, integrated with Tessent Streaming Scan Network (SSN), via Questa One DFT Simulation Acceleration
- 48x faster fault simulation, with support for functional safety and DFT use cases – enhanced by User Defined Fault Moderling (UDFM) via Tessent
- Stimulus-Free Verification, reducing analysis time from over 24 hours to under 1 minute on complex open source SoC level reference designs, using AI, 20+ integrated engines and tools like generative AI property creation
A Step Towards Smarter, Scalable Verification
Early adopters of Questa One are already seeing measurable improvements:
“The Questa One Smart Verification Solution has improved our verification productivity across traditional on-premises, and cloud deployments. As an early adopter of running large EDA workloads using the high-performance Questa One Sim advanced functional simulator, we’ve observed improvements in performance, cost-efficiency, and reduction in regression time on the latest AArch64 architecture,”
said Karima Dridi, Head of Productivity Engineering, Arm
Platforms like Questa One mark a significant shift towards intelligent, ecosystem-wide verification – bringing not just speed, but real scalability and actionable insights to the heart of the chip design process.
According to the official press release, Questa One will be available in June 2025. To learn more, visit the Siemens EDA website.