Discover how Synopsys is addressing design verification complexities in the AI era with advanced hardware-assisted verification solutions. … Read More
EDA
Accellera Approves Universal Verification Methodology for Mixed-Signal (UVM-MS) 1.0 Standard
Accellera Systems Initiative has officially approved the Universal Verification Methodology for Mixed-Signal (UVM-MS) 1.0 standard. This release is now available for immediate download. UVM-MS 1.0 establishes a standardized methodology for analog and mixed-signal (AMS) verification, building on the UVM IEEE 1800.2 standard. This methodology enhances AMS verification by enabling the reuse of proven components, leading to increased productivity, improved quality and streamlined workflows. … Read More
LPDDR6 Design & Test Workflow Solution Unveiled by Keysight
Keysight Technologies has launched a complete design and test solution for next-generation Low-Power Double Data Rate 6 (LPDDR6) memory technology. This solution helps engineers accelerate development, reduce design risks and improve product performance. Next-generation memory requires advanced testing to ensure reliability, speed and accuracy. Keysight’s LPDDR6 solution simplifies this process with high-precision, automated testing.
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DVCon U.S. 2025: Exploring the Future of Design and Verification
DVCon U.S. 2025, the premier conference for design and verification professionals, returns to San Jose, California, from February 24 – 27, 2025. Hosted at the DoubleTree by Hilton, the agenda will feature in-depth technical sessions, keynotes and panels, showcasing the latest advancements in verification methodologies, hardware design, low-power design and power optimization strategies. With a strong focus on chip design and the role of AI and ML in verification, attendees will be exploring how these ever-evolving technologies are transforming traditional processes. … Read More