On March 2nd 2026, Accellera Systems Initiative announced it has approved the Standard for IP Abstraction for Clock and Reset Domain Crossing Integration 1.0 for release and is now available for download. The new specification introduces a vendor-neutral mechanism for … Read More
Design & Verification
Autonomous Driving and Software-Defined Vehicles: Insights from EE Times Automotive Tech Forum 2026
Autonomous Driving and Software-Defined Vehicles: Insights from EE Times Automotive Tech Forum 2026 While electrification continues to reshape vehicle platforms, the real architectural shift in automotive is unfolding in autonomy and software-defined systems. At the EE Times Automotive Tech Forum … Read More
Cadence Unveils Chipstack AI Agentic Workflow for Design and Verification
Cadence ChipStack AI Super Agent Targets Front-End Design and Verification Cadence Design Systems has announced the launch of its ChipStack AI Super Agent, an agentic AI workflow designed to automate and accelerate front-end chip design and verification tasks. Announced on 10 February … Read More
UVM in Ireland: Training & Resources for Verification Engineers
Why UVM Matters in Ireland Universal Verification Methodology (UVM) has been a cornerstone of ASIC and SoC development for more than a decade. While new tools and techniques continue to emerge, UVM remains the industry standard for building scalable, reusable … Read More
Best On-Demand Semiconductor Webinars for Engineers (2025)
Staying ahead in semiconductor design means constantly learning – but not everyone has time for live events. This curated list brings together some of the best on-demand technical webinars from leading EDA vendors and semiconductor experts. ASIC & RTL Design Sharpen your … Read More
ASIC Design & Verification Research (2025): Technical Papers to Add to Your Reading List
Keeping up with the latest ASIC design and verification research can be overwhelming. From AI-driven automation and LLM-assisted RTL generation to high-throughput architectures and advanced security frameworks, 2025 has delivered remarkable breakthroughs. To save you time, we’ve curated some of … Read More
Stay Ahead in Semiconductors: Best YouTube Channels for ASIC Engineers
What YouTube Channels Should You Follow? YouTube has become one of the most valuable learning and discovery tools for engineers – especially in the ever-evolving world of semiconductors. Whether you’re interested in keeping up to date with the latest industry … Read More
What to Expect at DVCon Europe 2025: Topics, Tutorials and More
Your Quick Guide to DVCon Europe 2025 DVCon Europe 2025 kicks off this week, taking place October 14th – 15th in Munich, Germany, with the 10th SystemC Evolution Day following on October 16th. For engineers working in ASIC design, functional … Read More
Hardware-Assisted Verification: A Smarter Way to Accelerate Chip Development
Overcoming Bottlenecks in Modern Chip Development From AI accelerators to advanced SoCs, modern ASICs are growing more complex each year. Verification remains the most time-consuming and resource-intensive phase of the development process. According to industry sources such as AnySilicon, ASIC … Read More
ASIC vs FPGA: What Engineers Need to Know
ASICs and FPGAs are both essential parts of modern hardware design – but it’s important to understand that they solve different problems at different points in the silicon lifecycle. Whether you’re prototyping new IP or delivering final production, choosing between … Read More