DVCon Europe 2026: What to Expect and Key Deadlines for Open Call Submissions DVCon Europe is one of the most important events in the design and verification calendar, bringing together engineers, researchers and tool vendors focused on advancing verification methodologies. … Read More
Design & Verification
Upcoming Semiconductor Event Open Calls (2026): Key Deadlines for Design Verification Engineers
Planning to Present Your Work This Year? For engineers working across ASIC design, verification and hardware development, industry conferences remain one of the best ways to share insights, gain visibility and stay connected to the latest trends. From verification methodologies and SoC … Read More
World Quantum Day 2026: 3 Essential Reads on Quantum Verification for Hardware Engineers
World Quantum Day 2026: 3 Essential Reads on Quantum Verification for Hardware Engineers Each year, World Quantum Day (April 14th) highlights the rapid progress being made in quantum science. Over the past 12 months, we’ve seen continued momentum across the … Read More
Improve Your ASIC Verification Skills: Webinars for Semiconductor Engineers
Improve Your ASIC Verification Skills: Webinars for Semiconductor Engineers Staying current in ASIC verification is increasingly important as methodologies, tools, and design complexity continue to evolve. From established approaches like UVM and formal verification to newer areas such as AI-assisted … Read More
10 Best Semiconductor Podcasts for Engineers in 2026
10 Best Semiconductor Podcasts for Engineers in 2026 The semiconductor industry evolves at a relentless pace. New process nodes, AI-driven demand, chiplet architectures and shifting geopolitics are constantly reshaping how chips are designed and manufactured. Podcasts offer a simple way … Read More
Accellera Approves CDC/RDC Standard 1.0 for Release
On March 2nd 2026, Accellera Systems Initiative announced it has approved the Standard for IP Abstraction for Clock and Reset Domain Crossing Integration 1.0 for release and is now available for download. The new specification introduces a vendor-neutral mechanism for … Read More
Autonomous Driving and Software-Defined Vehicles: Insights from EE Times Automotive Tech Forum 2026
Autonomous Driving and Software-Defined Vehicles: Insights from EE Times Automotive Tech Forum 2026 While electrification continues to reshape vehicle platforms, the real architectural shift in automotive is unfolding in autonomy and software-defined systems. At the EE Times Automotive Tech Forum … Read More
Cadence Unveils Chipstack AI Agentic Workflow for Design and Verification
Cadence ChipStack AI Super Agent Targets Front-End Design and Verification Cadence Design Systems has announced the launch of its ChipStack AI Super Agent, an agentic AI workflow designed to automate and accelerate front-end chip design and verification tasks. Announced on 10 February … Read More
UVM in Ireland: Training & Resources for Verification Engineers
Why UVM Matters in Ireland Universal Verification Methodology (UVM) has been a cornerstone of ASIC and SoC development for more than a decade. While new tools and techniques continue to emerge, UVM remains the industry standard for building scalable, reusable … Read More
Best On-Demand Semiconductor Webinars for Engineers (2025)
Staying ahead in semiconductor design means constantly learning – but not everyone has time for live events. This curated list brings together some of the best on-demand technical webinars from leading EDA vendors and semiconductor experts. ASIC & RTL Design Sharpen your … Read More