If you work in ASIC design, verification or the broader Electronic Design Automation (EDA) ecosystem, DVCon Europe 2025 should be on your radar. Held in Munich, Germany on October 14 – 15, this year’s conference promises to deliver valuable insights, … Read More
EDA
Upcoming Semiconductor Events to Attend in North America (2025)
North America is home to some of the biggest and most influential semiconductor industry events on the global calendar. Our curated guide highlights key conferences, user group meetings and symposiums happening across the US throughout the rest of 2025. Whether … Read More
Siemens EDA Launches Questa One to Revolutionize Chip Verification
Siemens EDA Launches Questa One Verification Tool for Faster SoC Design At User2User in Munich, Siemens EDA unveiled Questa One – a unified, next-generation verification platform built to handle the rising complexity of SoC and ASIC designs in 2025 and … Read More
ASIC Design & Verification Glossary (2025 Edition)
This glossary covers essential terms and concepts in ASIC design, System-on-Chip (SoC) development and functional verification. Whether you’re a seasoned design verification engineer used to working with EDA tools or a recent graduate engineer getting started with UVM and SystemVerilog, … Read More
Synopsys at GTC 2025: Transforming Chip Design with NVIDIA GB200 Grace Blackwell Superchip
2025 is shaping up to be a landmark year for the EDA landscape. By leveraging cutting-edge AI and accelerated computing with the NVIDIA Grace Blackwell platform, Synopsys is focused on transforming chip design and powering the future of semiconductor innovation. … Read More
Synopsys Unveils Advanced Hardware-Assisted Verification Solutions: ZeBu-200 & HAPS-200
Discover how Synopsys is addressing design verification complexities in the AI era with advanced hardware-assisted verification solutions. … Read More
Accellera Approves Universal Verification Methodology for Mixed-Signal (UVM-MS) 1.0 Standard
Accellera Systems Initiative has officially approved the Universal Verification Methodology for Mixed-Signal (UVM-MS) 1.0 standard. This release is now available for immediate download. UVM-MS 1.0 establishes a standardized methodology for analog and mixed-signal (AMS) verification, building on the UVM IEEE 1800.2 standard. This methodology enhances AMS verification by enabling the reuse of proven components, leading to increased productivity, improved quality and streamlined workflows. … Read More
LPDDR6 Design & Test Workflow Solution Unveiled by Keysight
Keysight Technologies has launched a complete design and test solution for next-generation Low-Power Double Data Rate 6 (LPDDR6) memory technology. This solution helps engineers accelerate development, reduce design risks and improve product performance. Next-generation memory requires advanced testing to ensure reliability, speed and accuracy. Keysight’s LPDDR6 solution simplifies this process with high-precision, automated testing.
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DVCon U.S. 2025: Exploring the Future of Design and Verification
DVCon U.S. 2025, the premier conference for design and verification professionals, returns to San Jose, California, from February 24 – 27, 2025. Hosted at the DoubleTree by Hilton, the agenda will feature in-depth technical sessions, keynotes and panels, showcasing the latest advancements in verification methodologies, hardware design, low-power design and power optimization strategies. With a strong focus on chip design and the role of AI and ML in verification, attendees will be exploring how these ever-evolving technologies are transforming traditional processes. … Read More