If you work in ASIC design, verification or the broader Electronic Design Automation (EDA) ecosystem, DVCon Europe 2025 should be on your radar. Held in Munich, Germany on October 14 – 15, this year’s conference promises to deliver valuable insights, … Read More
Verification
Siemens EDA Launches Questa One to Revolutionize Chip Verification
Siemens EDA Launches Questa One Verification Tool for Faster SoC Design At User2User in Munich, Siemens EDA unveiled Questa One – a unified, next-generation verification platform built to handle the rising complexity of SoC and ASIC designs in 2025 and … Read More
ASIC Design & Verification Glossary (2025 Edition)
This glossary covers essential terms and concepts in ASIC design, System-on-Chip (SoC) development and functional verification. Whether you’re a seasoned design verification engineer used to working with EDA tools or a recent graduate engineer getting started with UVM and SystemVerilog, … Read More
What is UVM? A Beginner’s Guide to Universal Verification Methodology
At the core of our verification process lies the powerful Universal Verification Methodology (UVM). This industry-standard methodology empowers us to deliver exceptional quality and efficiency in design verification. By harnessing the standardized framework of UVM, we ensure thorough and reliable … Read More
Top Resources for ASIC Design & Verification Engineers (2025 Edition)
Searching for the Top Resources for ASIC Design & Verification Engineers? Whether you’re just getting started with ASIC design or you’re deep into verifying complex chips, staying up to date with the latest knowledge, tools and thought leadership is essential. … Read More
DVCon U.S. 2025: Exploring the Future of Design and Verification
DVCon U.S. 2025, the premier conference for design and verification professionals, returns to San Jose, California, from February 24 – 27, 2025. Hosted at the DoubleTree by Hilton, the agenda will feature in-depth technical sessions, keynotes and panels, showcasing the latest advancements in verification methodologies, hardware design, low-power design and power optimization strategies. With a strong focus on chip design and the role of AI and ML in verification, attendees will be exploring how these ever-evolving technologies are transforming traditional processes. … Read More