Your Quick Guide to DVCon Europe 2025 DVCon Europe 2025 kicks off this week, taking place October 14th – 15th in Munich, Germany, with the 10th SystemC Evolution Day following on October 16th. For engineers working in ASIC design, functional … Read More
Verification
Semiconductor News: September 2025 Roundup
Strategic Partnerships and Semiconductor Innovation From OpenAI’s rumoured chip venture to a 3DIC test chip tape-out by Alchip and new university chip design initiatives, September 2025 was packed with developments across the semiconductor world. We’ve curated the month’s most relevant … Read More
Hardware-Assisted Verification: A Smarter Way to Accelerate Chip Development
Overcoming Bottlenecks in Modern Chip Development From AI accelerators to advanced SoCs, modern ASICs are growing more complex each year. Verification remains the most time-consuming and resource-intensive phase of the development process. According to industry sources such as AnySilicon, ASIC … Read More
ASIC vs FPGA: What Engineers Need to Know
ASICs and FPGAs are both essential parts of modern hardware design – but it’s important to understand that they solve different problems at different points in the silicon lifecycle. Whether you’re prototyping new IP or delivering final production, choosing between … Read More
Semiconductor News Roundup: Industry Highlights (May – July 2025)
Welcome to the first edition of our Semiconductor News Roundup! In an ever-evolving industry, this is your essential summary of the latest updates in chip design, verification and semiconductor innovation. This edition covers highlights from May to July 2025, including … Read More
DVCon Europe 2025: Submission Deadlines, Key Themes & How to Get Involved
If you work in ASIC design, verification or the broader Electronic Design Automation (EDA) ecosystem, DVCon Europe 2025 should be on your radar. Held in Munich, Germany on October 14 – 15, this year’s conference promises to deliver valuable insights, … Read More
Siemens EDA Launches Questa One to Revolutionize Chip Verification
Siemens EDA Launches Questa One Verification Tool for Faster SoC Design At User2User in Munich, Siemens EDA unveiled Questa One – a unified, next-generation verification platform built to handle the rising complexity of SoC and ASIC designs in 2025 and … Read More
ASIC Design & Verification Glossary (2025 Edition)
This glossary covers essential terms and concepts in ASIC design, System-on-Chip (SoC) development and functional verification. Whether you’re a seasoned design verification engineer used to working with EDA tools or a recent graduate engineer getting started with UVM and SystemVerilog, … Read More
What is UVM? A Beginner’s Guide to Universal Verification Methodology
At the core of our verification process lies the powerful Universal Verification Methodology (UVM). This industry-standard methodology empowers us to deliver exceptional quality and efficiency in design verification. By harnessing the standardized framework of UVM, we ensure thorough and reliable … Read More
Top Resources for ASIC Design & Verification Engineers (2025 Edition)
Searching for the Top Resources for ASIC Design & Verification Engineers? Whether you’re just getting started with ASIC design or you’re deep into verifying complex chips, staying up to date with the latest knowledge, tools and thought leadership is essential. … Read More